(Conventional Complementary MISFET)
Integrated circuits constituted of complementary MISFET's having features of lower power consumption, higher integration density, and the like are widely used for a portable type of battery-driven electronic equipment and the like.
FIG. 28(a) is a cross-sectional view showing a structure of a conventional complementary MISFET formed on a planar substrate. The conventional complementary MISFET is constituted of a P-type MISFET formed on an N-type well region 492 and an N-type MISFET formed on a P-type substrate 491. The P-type MISFET is constituted of a gate electrode 499, a P-type drain region 495, and a P-type source region 494, and the source region 494 and well region 492 are electrically connected with each other via an N-type well contact region 493. The N-type MISFET is constituted of a gate electrode 500, an N-type drain region 496, and an N-type source region 497, and the source region 497 and substrate 491 are electrically connected with each other via a P-type substrate contact region 498.
(Conventional Integrated Circuit)
There will be explained structures and functions of a semiconductor memory, an image sensor, and a PLA, as examples of conventional integrated circuits.
(Conventional Semiconductor Memory)
Semiconductor memories are widely used in computers, electronic equipment, and the like, as apparatus for storing electronic information such as programs and data.
FIG. 24(a) is a cross-sectional view of MISFET's formed on a planar substrate constituting a conventional semiconductor memory. Formed on a planar substrate 401 made of silicon or the like, are a plurality of MISFET's comprising gate electrodes 403, gate insulating films 404, source regions 405, and drain regions 406, respectively, in a manner electrically separated by insulative separation regions 402, respectively, formed by a LOCOS method or the like.
FIG. 24(b) is a circuit diagram of a semiconductor memory such as a masked ROM, and FIGS. 25(a) and (b) are plan views of the conventional semiconductor memory corresponding to the circuit diagram shown in FIG. 24(b). In FIGS. 25(a) and (b), each MISFET is constituted of a pattern of a gate electrode, a source region, a drain region, a source contact, and a drain contact. For example, the MISFET arranged at the upper left of FIG. 25(a) is constituted of a pattern of a gate electrode 421, a source region 422, a drain region 423, a source contact 424, and a drain contact 425. The MISFET's are connected to one another by gate wirings such as made of polycrystalline silicon, and source wirings and drain wirings such as made of Al. In FIGS. 25(a) and (b), the gate wirings 421, 431 are formed of a polycrystalline silicon layers common to the gate electrodes, and correspond to word lines 411 of FIG. 24(b), respectively. Both source wirings 426, 436 are connected to a ground potential. Drain wirings 427, 437 correspond to bit lines 412 of FIG. 24(b), respectively.
Recording of information in a masked ROM is achieved by connecting or unconnecting drains and bit lines. FIG. 24(b) shows a connected node 413 where a drain and a bit line 412 is connected, and an unconnected node 414 where a drain and the bit line 412 is unconnected. The planar substrate 401 is to be prepared in a state completed up to MISFET's and a first layer of Al wirings (source wirings). At a stage where data to be stored in the masked ROM is determined, there is prepared a mask of drain contacts 425 or a mask of a second layer of Al wirings 437 to thereby realize a combined logic circuit even by a small number of masking steps, thereby enabling a shortened turn-around-time. FIG. 25(a) corresponds a situation where data has been recorded by a pattern of drain contacts, and FIG. 25(b) corresponds to a situation where data has been stored by a pattern of a second layer of Al wirings.
(Conventional Image Sensor)
Image sensors are each constituted of photodiodes for converting light energy into electrical energy, and MISFET's for accumulating generated electrical energies and for taking them out as electrical signals, and each include one-dimensionally or two-dimensionally arranged pixels having combined photodiodes and MISFET's, respectively, to exhibit a function for taking out light-beams sensed by the pixels as image signals, respectively.
FIG. 26(a) is a cross-sectional view of a MISFET and a photodiode formed on a planar substrate constituting a conventional image sensor, (b) is a part of a circuit diagram of the image sensor, and (c) is a plan view of the conventional image sensor corresponding to (b). Formed on a P-type planar substrate 451 such as made of silicon, are: a MISFET constituted of a gate electrode 456, a gate insulating film 455, an N-type source region 453, and an N-type drain region 454; and a photodiode constituted of the P-type planar substrate 451 and an N-type cathode region 459.
FIG. 26(b) is a circuit diagram of the image sensor, and FIG. 26(c) is a plan view of the conventional image sensor corresponding to the circuit diagram shown in FIG. 26(b). Photodiodes 462 and MISFET's 463 of FIG. 26(b) correspond to patterns 466 and patterns 467 of FIG. 26(c), respectively, and a vertical selection line 464 of FIG. 26(b) corresponds to a gate electrode simultaneously serving as a gate wiring of FIG. 26(c). Further, vertical signal lines 465 of FIG. 26(b) correspond to drain wirings 469 of FIG. 26(c), respectively. Connecting the substrate 451 to a ground potential connects anodes of the photodiodes to the ground potential. Irradiation of light to PN junctions constituting the photodiodes generates electron-positive hole pairs, and generated electrons pass through the N-type cathode regions of the MISFET's and are accumulated in the source regions 453 thereof, respectively. When the MISFET's are turned ON by control of gate voltages, accumulated electrons pass through the drain wirings and transferred to an output circuit of the image sensor.
(Conventional PLA)
PLA's are logic integrated circuits effective for automatized layout design and shortened turn-around-time of design, since arbitrary combined logics can be realized by simply changing wiring patterns on an integrated circuit comprising orderly arranged multiple MISFET's.
FIG. 24(a) is a cross-sectional view of MISFET's formed on a planar substrate constituting a conventional PLA. Formed on a planar substrate 401 made of silicon or the like, are a plurality of MISFET's comprising gate electrodes 403, gate insulating films 404, source regions 405, and drain regions 406, respectively, in a manner electrically separated by insulative separation regions 402, respectively, formed by a LOCOS method or the like.
FIG. 27(a) is a circuit diagram of an AND plane of the PLA, and FIG. 27(b) is a plan view of the conventional PLA corresponding to the circuit diagram shown in FIG. 27(a). Each MISFET is constituted of a pattern of a gate electrode, a source region, a drain region, a source contact, and a drain contact. For example, the MISFET arranged at the upper left of FIG. 27(b) is constituted of a pattern of a gate electrode 474, a source region 475, a drain region 476, a source contact 477, and a drain contact 478. The MISFET's are connected to one another by gate wirings such as made of polycrystalline silicon, and source wirings and drain wirings such as made of Al. In FIG. 27(b), the gate wirings 479 are formed of a polycrystalline silicon layer common to the gate electrodes, and correspond to AND plane input wirings 471 of FIG. 27(a), respectively. All source wirings 480 are connected to a ground potential. Drain wirings 481 correspond to AND plane output wirings 473 of FIG. 27(a), respectively. The planar substrate 401 is to be prepared in a state completed up to MISFET's and a first layer of Al wirings. At a stage where a system to be realized by an integrated circuit is determined, there is prepared a mask of a second layer of Al wirings to thereby realize a combined logic circuit only by one step of masking, thereby enabling a shortened turn-around-time.